1. Field of the Invention
This invention relates generally to a clock recovery system for synchronizing color graphic image display. More particularly, this invention relates to an intelligent and independent analog signal interface controller provided with self-alignment to analogy signals and intelligent and dynamic phase tracking for continuous periodical clock recovery.
2. Description of the Prior Art
Several technical difficulties are faced by those who apply state of art technology in providing a LCD control card to display color images on a liquid crystal display (LCD) panel. These technical difficulties are caused by many uncharacterized factors now exist in current technology for analog-digital signal interfaces. Specifically, these uncharacterized factors are resulting from 1) the frequency f1 of the analog signals from the graphic card is not available to the LCD control card; 2) the jitters of the phase shift between frequency f1 of the graph card and the LCD control card f2, especially the long term jitters generated by phase shifts in two separate systems; 3) analog signal distortions in transmitting from the graphic card to the LCD control card; 4) HSYNC (n f1) received from graphic control card is non-integral clock cycles of local clock (f2) since f2 is not exactly equal to f1; 5) relative frequency shift; and 6) the uncharacterized timing relationship between a horizontal synchronization signal (HSYNC) and the analog RGB signals. These technical difficulties lead to several design and image display problems, which are not resolved by those of ordinary skill in the art.
A first problem encountered by a LCD control card designer is the difficulties in dealing with the sampling of the analog signals. Due to these uncharacterized factors, sampling of analog signals becomes very sensitive to clock phase, clock jitter, and clock accuracy. However, jitters generated by relative frequency and relative phase shifts prevent accurate sampling of the analog signals. This leads to poor display image quality and degraded performance in processing the analog signals by an LCD control card. Image distortions in space, time and gray scale are produced due to sampling errors. Uneven and blurred edges are shown on vertical lines in displaying the images. Loss of edge sharpness of the graphic images is produced. Uneven sampling from frame to frame is also a problem caused by variations of the analog RGB data received from the graphic controller. Several systems are now available in the market in attempt to resolve these problems by a method of manually make an on-screen selection (OSD). But an OSD manual adjustment cannot handle the more dynamic variations and cannot optimize the phase margins due to the limitations that human eyes cannot identify 180 phase of the RGB signals. The phase margin selected by the OSD method cannot assure sufficient margins are provided to cover different conditions that may cause the frequency and phase to shift.
In an A/D converter provided by Genlock, for video application, the incoming video stream signals are tracked to detect the SYNC signals. As the SYNC signals are in synchronization with the phase of the incoming video signals, the detected SYNC signals are employed to generate a new clock phase to line-up with the video signal phase. Since the SYNC signals must be generated separately, standard output signals provided by regular CRT graphic cards cannot be included in by a LCD control card implemented with Genlock converter.
In a system provided by Read/Write Channel, the digital data are coded. Transitions of digital data can be easily detected. A pulse can be generated in alignment with a transition of digital data. The pulse can be employed as a reference phase for aligning the clock phase. The frequency is then determined by applying the elapsed time between the pulses generated according to the digital data transitions. Again, as that incurred in Genlock system, the coded digital data must be generated separately, standard output signals provided by regular CRT graphic cards cannot be employed directly by an LCD control card implemented with Read/Write clock recovery system.
Therefore, a need still exists in the art of digital flat-panel image display to provide a clock recovery system and method to resolve the problems discussed above. Specifically, it is desirable to provide a novel method and an intelligent clock recovery system to achieve self-alignment between the clock and the RGB image data. It is further desirable that the self-alignment with the RGB data can be achieved by employing a standard RGB DIN connector used for conventional CRT display. Connectors for regular CRT can be directly employed for connecting to a LCD graphic control card for a digital LCD monitor without requiring a separate signal processor and data transceiver as that required in Genlock and Read/Write Channel such that simple and low cost implementation can be achieved.
It is therefore an object of the present invention to provide a new clock recovery system without relying on clock signals provided from a RAMDAC card. Therefore, the aforementioned difficulties and limitations caused by uncharacterized parameters in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new configuration and method for a clock recovery system where the phase and frequency are determined by employing the real time image data. The uncertainties and distortions caused by phase and frequency drifts and deviations caused by random phase, jitters over a period of time between real-time analog data and local generated clock for A/D converter are eliminated.
Another object of the present invention is to provide a new clock-recovery system implemented with novel configuration and method where an automatic phase alignment to the incoming RGB signals and HSYNC are performed dynamically and automatically. The technical difficulties leading to poor quality of video images caused by the uncharacterized parameters as discussed above are therefore eliminated.
Another object of the present invention is to provide new clock-recovery system implemented with novel configuration and method where an automatic phase alignment to the incoming RGB signals and HSYNC is performed at 180"Ugr" of the RGB signals to allow more phase variations due to inaccurate frequency from the RAMDAC clock Greater tolerances for RAMDAC frequency inaccuracies are provided without causing additional deviations of phase alignment within the greater tolerance limits.
Another object of the present invention is to provide a new clock-recovery system implemented with novel configuration and method where an automatic phase alignment to the incoming RGB signals and HSYNC are performed dynamically and automatically. Conventional on-screen-selection (OSD) to align the phase by a manual tuning is no longer necessary and can be provided only as an option. The manual phase tuning can be provided to override the automatically phase alignment according to a user""s preference if an OSD option is selected.
Briefly, in a preferred embodiment, the present invention discloses a clock recovery system for aligning a clock-phase with RGB signals. The clock recovery system includes a voltage transition detector for detecting consecutive voltage transitions from receiving the RGB signals. The clock recovery system further includes a phase-selection means for applying the times detected for the voltage transitions for latching the clock-phase of the A/D converter to a phase angle of the RGB signals. In a preferred embodiment, the clock-phase of the A/D converter is latched to a half-cycle phase, i.e., 180"Ugr" phase-angle, according to the detected times of the voltage transitions from receiving the RGB signals. The time recovery system further includes a RGB analog signal sensor tracking with an preamplifier of an A/D converter. It further includes a digital phase lock loop (PLL) for carrying out a dynamic RGB phase-segment selection update for adjusting the A/D clock by making a left-or-right phase-shift operation to dynamically and continuously correct random phase jitters.
In a specific embodiment, this invention discloses a clock recovery system for aligning a clock-phase with RGB signals. The clock recovery system includes a frequency-synthesizing loop for receiving a reference clock signal (CKREF) to generate a synthesized frequency. The clock recovery system further includes a fine-tuned frequency synthesizing loop for receiving a horizontal synchronization signal (HSYNC) to fine tune the synthesized frequency into a fine-tuned synthesized frequency. The clock recovery system further includes a phase divider for subdividing the fine-tuned synthesized frequency into a multiple phase segments for inputting to the multiplex controller. The clock recovery system further includes a multiplex controller for receiving the multiple phase-segments subdivided. The clock recovery system further includes an analog sensor for receiving and sensing the RGB signals for generating encoded sensing data corresponding to voltage transitions of the RGB signals. The clock recovery system further includes a transition detection means for applying the encoded sensing data for generating transition-detection data. The clock recovery system further includes a threshold triggering circuit for comparing the transition-detection data with a threshold data and triggering a RGB-phase data upon detecting the threshold data is exceeded by the transition detection data. The clock recovery system further includes a phase sampling means for applying the RGB-phase data for selecting a clock-alignment phase-segment from one of the multiple phase segments received from the multiplex controller for aligning the clock-phase. The clock recovery system further includes a digital phase-lock loop (PLL) includes a phase shift-direction detector (PD) for receiving the RGB-phase data from the threshold triggering circuit and the clock-alignment phase-segment from the multiplex controller for generating a dynamic phase-shift difference. The digital PLL further includes a digital filter for receiving the dynamic phase-shift difference from the PD for generating a phase-segment-shift signal for outputting to the multiplex controller for shifting the clock-alignment phase-segment to dynamically align the clock-phase. This invention also discloses a method of processing red-green-blue (RGB) analog signals for converting said RGB analog signals to corresponding digital signals for image display. The method includes the steps of a) receiving a reference clock (CKREF) signal as a digital signal; b) generating a synthesized frequency (f2) by applying a phase-locking operation for locking a phase of the synthesized frequency with the reference clock (CKREF) signal; c) receiving horizontal synchronization (HSYN) signals as digital signals and generating a fine-tuned synthesized frequency (f2xe2x80x2) by performing a phase locking operation to lock a phase of the fine tuned synthesized frequency with the HSYN signals; d) dividing the fine-tuned synthesized frequency (f2xe2x80x2) into Nxe2x80x2-equal phase-segments where Nxe2x80x2 is a positive integer; e) detecting at least two voltage transitions from receiving a series of the RGB analog signals and generating a clock-phase select signal for automatically selecting an auto-selected phase-segment among the Nxe2x80x2-equal phase-segments for latching the fine-tuned synthesized frequency (f2xe2x80x2); and f) periodically detecting voltage transitions from receiving a series of the RGB analog signals after a predefined elapsed-time and generating a dynamic clock-phase select signal for periodically selecting an auto-selected phase-segment among the N-equal phase-segments to for latching the fine-tuned synthesized frequency (f2xe2x80x2). In a preferred embodiment, the method further includes a step of g) providing a static phase adjusting means to allow a user to select a user-selected phase segment among the Nxe2x80x2-equal phase-segments to for latching the fine-tuned synthesized frequency (f2xe2x80x2).
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.